Figure 415. Receive Fifo Read Task - STMicroelectronics STM32F405 Reference Manual

RM0090
•
Bulk and control OUT/SETUP transactions
A typical bulk or control OUT/SETUP pipelined transaction-level operation is shown in
Figure
SETUP transaction operates in the same way but has only one packet. The
assumptions are:
–
–
–
•
Normal bulk and control OUT/SETUP operations
The sequence of operations for channel 1 is as follows:
a)
b)
c)
d)
e)
f)
g)
h)

Figure 415. Receive FIFO read task

Unmask RXFLVL
interrupt
Read the received
packet from the
Receive FIFO
Yes
416. See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control
The application is attempting to send two maximum-packet-size packets (transfer
size = 1, 024 bytes).
The nonperiodic transmit FIFO can hold two packets (128 bytes for FS).
The nonperiodic request queue depth = 4.
Initialize channel 1
Write the first packet for channel 1
Along with the last DWORD write, the core writes an entry to the nonperiodic
request queue
As soon as the nonperiodic queue becomes nonempty, the core attempts to send
an OUT token in the current frame
Write the second (last) packet for channel 1
The core generates the XFRC interrupt as soon as the last transaction is
completed successfully
In response to the XFRC interrupt, de-allocate the channel for other transfers
Handling nonACK responses
DocID018909 Rev 11
USB on-the-go high-speed (OTG_HS)
Start
No
RXFLVL
interrupt ?
Yes
Mask RXFLVL Unmask RXFLVL
interrupt
Read
OTG_FS_GRXSTSP
PKTSTS
No
0b0010?
Yes
BCNT > 0?
interrupt
No
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