Rtc Date Register (Rtc_Dr) - STMicroelectronics STM32F405 Reference Manual

RM0090
26.6.2

RTC date register (RTC_DR)

The RTC_DR is the calendar date shadow register. This register must be written in
initialization mode only. Refer to
Reading the calendar on page
Address offset: 0x04
Backup domain reset value: 0x0000 2101
System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
31 30 29
15 14 13
WDU[2:0]
rw rw rw
Bits 31-24 Reserved
Bits 23:20 YT[3:0]: Year tens in BCD format
Bits 19:16 YU[3:0]: Year units in BCD format
Bits 15:13 WDU[2:0]: Week day units
000: forbidden
001: Monday
...
111: Sunday
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format
Note: This register is write protected. The write access procedure is described in
write protection on page
28 27 26 25
Reserved
12 11 10 9
MT MU[3:0]
rw rw rw rw
794.
DocID018909 Rev 11
Calendar initialization and configuration on page 794
795.
24 23 22
YT[3:0]
rw rw
8 7 6
Reserved
rw
Real-time clock (RTC)
21 20 19 18
YU[3:0]
rw rw rw rw
5 4 3 2
DT[1:0] DU[3:0]
rw rw rw rw
RTC register
and
17 16
rw rw
1 0
rw rw
807/1731
828