Table 75. External Triggers; Figure 67. Timing Diagram For Conversion With Trigger Disabled Ten = 0; Dac Output Voltage - STMicroelectronics STM32F405 Reference Manual

RM0090

Figure 67. Timing diagram for conversion with trigger disabled TEN = 0

APB1_CLK
14.3.5

DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and V
The analog output voltages on each DAC channel pin are determined by the following
equation:
DACoutput
14.3.6 DAC trigger selection
If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8
possible events will trigger conversion as shown in
Timer 6 TRGO event
Timer 8 TRGO event
Timer 7 TRGO event
Timer 5 TRGO event
Timer 2 TRGO event
Timer 4 TRGO event
EXTI line9
SWTRIG
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on
the selected external interrupt line 9, the last data stored into the DAC_DHRx register are
transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1
cycles after the trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
DHR 0x1AC
DOR
DOR
× ------------- -
= V
REF
4095

Table 75. External triggers

Source
Internal signal from on-chip
timers
External pin
Software control bit
DocID018909 Rev 11
Digital-to-analog converter (DAC)
0x1AC
t
SETTLING
Table 75.
Type
Output voltage
available on DAC_OUT pin
ai14711b
TSEL[2:0]
000
001
010
011
100
101
110
111
439/1731
.
REF+
456