Figure 81. Ltdc Block Diagram; Ltdc Functional Description - STMicroelectronics STM32F405 Reference Manual

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16.3

LTDC functional description

16.3.1 LTDC block diagram
The block diagram of the LTDC is shown in
Layer FIFO: One FIFO 64x32 bit per layer.
PFC: Pixel Format Convertor performing the pixel format conversion from the selected input
pixel format of a layer to words.
AHB interface: For data transfer from memories to the FIFO.
Blending, Dithering unit and Timings Generator: Refer to
16.3.2 LTDC reset and clocks
The LCD-TFT controller peripheral uses 3 clock domains:
•
The AHB clock domain (HCLK): for data transfer from the memories to the Layer FIFO
•
The APB2 clock domain (PCLK2): for register configuration
•
The Pixel Clock domain (LCD_CLK): to generate LCD-TFT interface signals. The
LCD_CLK output should be configured following the panel requirements. The
LCD_CLK is configured through the PLLSAI (refer to RCC section)
The LCD controller can be reset by setting the corresponding bit in the RCC_APB2RSTR
register. It resets the three clock domains.
Figure 81: LTDC block

Figure 81. LTDC block diagram

DocID018909 Rev 11
LCD-TFT Controller (LTDC)
diagram.
Section 16.4.1 and Section 16.4.2.
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