Table 295. Jtag Debug Port Data Registers; Boundary Scan Tap - STMicroelectronics STM32F405 Reference Manual

Debug support (DBG)
38.6.2

Boundary scan TAP

JTAG ID code
The TAP of the STM32F4xx BSC (boundary scan) integrates a JTAG ID code equal to .
•
0x06413041 for STM32F405xx/07xx and STM32F415xx/17xx devices
• 0x06419041 for STM32F42xxx and STM32F43xxx devices
38.6.3 Cortex
The TAP of the ARM
®
ARM default one and has not been modified. This code is only accessible by the JTAG
Debug Port.
This code is 0x4BA00477 (corresponds to Cortex
Reference ARM®
38.6.4 Cortex
The ARM
ROM table mapped on the internal PPB bus at address 0xE00FF000_0xE00FFFFF.
This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two
pins) or by the user software.
38.7 JTAG debug port
A standard JTAG state machine is implemented with a 4-bit instruction register (IR) and five
data registers (for full details, refer to the Cortex
Manual (TRM), for references, please see
IR(3:0)
1111
1110
1678/1731
®
-M4 with FPU TAP
® ®
Cortex
documentation).
®
-M4 with FPU JEDEC-106 ID code
® ®
Cortex -M4 with FPU integrates a JEDEC-106 ID code. It is located in the 4KB

Table 295. JTAG debug port data registers

Data register
BYPASS
[1 bit]
IDCODE ID CODE
[32 bits] 0x4BA00477 (ARM
DocID018909 Rev 11
-M4 with FPU integrates a JTAG ID code. This ID code is the
®
-M4 with FPU r0p1, see
®
-M4 with FPU r0p1 Technical Reference
Section 38.2: Reference ARM®
® ®
Cortex -M4 with FPU
Section 38.2:
documentation).
Details
r0p1
ID Code)
RM0090