Table 106. Min/Max Iwdg Timeout Period At 32 Khz (Lsi); Figure 213. Independent Watchdog Block Diagram; Debug Mode - STMicroelectronics STM32F405 Reference Manual

Independent watchdog (IWDG)
with a different value will break the sequence and register access will be protected again.
This implies that it is the case of the reload operation (writing 0xAAAA).
A status register is available to indicate that an update of the prescaler or the down-counter
reload value is on going.
21.3.3

Debug mode

When the microcontroller enters debug mode (Cortex
counter either continues to work normally or stops, depending on DBG_IWDG_STOP
configuration bit in DBG module. For more details, refer to
for timers, watchdog, bxCAN and
Note: The watchdog function is implemented in the V
Stop and Standby modes.
Prescaler divider
/16
/32
/64
/128
/256
1. These timings are given for a 32 kHz clock but the microcontroller internal RC frequency can vary. Please
refer to the LSI oscillator characteristics table in the device datasheet for maximum and minimum values.
700/1731

Figure 213. Independent watchdog block diagram

Table 106. Min/max IWDG timeout period at 32 kHz (LSI)

PR[2:0] bits
/4 0
/8 1
2
3
4
5
6
DocID018909 Rev 11
®
-M4 with FPU core halted), the IWDG
I2C.
voltage domain that is still functional in
DD
Min timeout (ms) RL[11:0]=
0x000
0.125
0.25
0.5
1
2
4
8
Section 38.16.2: Debug support
(1)
Max timeout (ms) RL[11:0]=
0xFFF
512
1024
2048
4096
8192
16384
32768
RM0090