Dma2D Foreground Color Register (Dma2D_Fgcolr) - STMicroelectronics STM32F405 Reference Manual

Chrom-Art Accelerator™ controller (DMA2D)
11.5.9

DMA2D foreground color register (DMA2D_FGCOLR)

Address offset: 0x0020
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
GREEN[7:0]
rw rw rw rw
Bits 31:24 Reserved, must be kept at reset value
Bits 23:16 RED[7: 0]: Red Value
Bits 15:8 GREEN[7: 0]: Green Value
Bits 7:0 BLUE[7: 0]: Blue Value
362/1731
27 26 25
Reserved
11 10 9
rw rw rw
These bits defines the red value for the A4 or A8 mode of the foreground image. They
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
These bits defines the green value for the A4 or A8 mode of the foreground image. They
can only be written when data transfers are disabled. Once the transfer has started,
They are read-only.
These bits defines the blue value for the A4 or A8 mode of the foreground image. They
can only be written when data transfers are disabled. Once the transfer has started,
They are read-only.
DocID018909 Rev 11
24 23 22 21
rw rw rw
8 7 6 5
rw rw rw rw
20 19 18 17
RED[7:0]
rw rw rw rw
4 3 2 1
BLUE[7:0]
rw rw rw rw
RM0090
16
rw
0
rw