Table 198. Data Fifo (Dfifo) Access Register Map; Table 199. Power And Clock Gating Control And Status Registers - STMicroelectronics STM32F405 Reference Manual

RM0090
Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access
Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access
Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access
Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access
...
Device IN Endpoint x
Device OUT Endpoint x
1. Where x is 3 in device mode and 7 in host mode.
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and device
modes.
Power and clock gating control register
Reserved

Table 198. Data FIFO (DFIFO) access register map

FIFO access register section
(1)
/Host OUT Channel x
(1)
/Host IN Channel x

Table 199. Power and clock gating control and status registers

Register name
DocID018909 Rev 11
USB on-the-go full-speed (OTG_FS)
(1)
: DFIFO Write Access
(1)
: DFIFO Read Access
Acronym Offset address: 0xE00–0xFFF
PCGCR 0xE00-0xE04
0xE05–0xFFF
Address range Access
w
0x1000–0x1FFC
r
w
0x2000–0x2FFC
r
... ...
w
0xX000–0xXFFC
r
1261/1731
1368