General Timing Rules - STMicroelectronics STM32F405 Reference Manual

RM0090
Table 220. NOR Flash/PSRAM controller: example of supported memories
Device
PSRAM
(multiplexed
I/Os and
nonmultiplexed
I/Os)
SRAM and
ROM
36.5.3

General timing rules

Signals synchronization
• All controller output signals change on the rising edge of the internal clock (HCLK)
•
In synchronous mode (read or write), all output signals change on the rising edge of
HCLK. Whatever the CLKDIV value, all outputs change as follows:
–
–
and transactions (continued)
Mode
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous
page
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FSMC_CLK clock.
NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FSMC_CLK clock.
DocID018909 Rev 11
Flexible static memory controller (FSMC)
AHB
Memory
R/W data
data size
size
8 16
8 16
16 16
16 16
32 16
32 16
R - 16
R 8 16
R 16 16
R 32 16
W 8 16
W 16/32 16
8 / 16 16
8 / 16 16
32 16
32 16
Allowed/
not Comments
allowed
Y
Y Use of byte lanes NBL[1:0]
Y
Y
Y Split into 2 FSMC accesses
Y Split into 2 FSMC accesses
N Mode is not supported
N
Y
Y
Y Use of byte lanes NBL[1:0]
Y
Y
Y Use of byte lanes NBL[1:0]
Y Split into 2 FSMC accesses
Split into 2 FSMC
accesses.
Y
Use of byte lanes NBL[1:0]
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