Table 298. Ack Response (3 Bits); Table 299. Data Transfer (33 Bits); Sw-Dp State Machine (Reset, Idle States, Id Code) - STMicroelectronics STM32F405 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

Refer to the Cortex

APACC registers.

The packet request is always followed by the turnaround time (default 1 bit) where neither

the host nor target drive the line.

The ACK Response must be followed by a turnaround time only if it is a READ transaction

or if a WAIT or FAULT acknowledge has been received.

The DATA transfer must be followed by a turnaround time only if it is a READ transaction.

The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It

follows the JEP-106 standard. This ID code is the default ARM

0x2BA01477 (corresponding to Cortex

Note that the SW-DP state machine is inactive until the target reads this ID code.

The SW-DP state machine is in RESET STATE either after power-on reset, or after the

DP has switched from JTAG to SWD or after the line is high for more than 50 cycles

The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles

after RESET state.

After RESET state, it is mandatory to first enter into an IDLE state AND to perform a

READ access of the DP-SW ID CODE register. Otherwise, the target will issue a

FAULT acknowledge response on another transactions.

Table 297. Packet request (8-bits) (continued)

Address field of the DP or AP registers (refer to

Single bit parity of preceding bits

Not driven by the host. Must be read as "1" by the target because of

-M4 with FPUr0p1 TRM for a detailed description of DPACC and

Table 298. ACK response (3 bits)

WDATA or RDATA Write or Read data

Single parity of the 32 data bits

DocID018909 Rev 11

-M4 with FPU r0p1).

Debug support (DBG)

one and is set to

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