Syscfg External Interrupt Configuration Register - STMicroelectronics STM32F405 Reference Manual

RM0090
Bits 22:19 Reserved, must be kept at reset value.
Bits 18:16 ADCxDC2:
Bits 15:0 Reserved, must be kept at reset value.
9.3.3

SYSCFG external interrupt configuration register 1

(SYSCFG_EXTICR1)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
15 14 13
EXTI3[3:0]
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Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)
0: No effect.
1: Refer to AN4073 on how to use this bit.
Note: These bits can be set only if the following conditions are met:
- ADC clock higher or equal to 30 MHz.
- Only one ADCxDC2 bit must be selected if ADC conversions do not start
at the same time and the sampling times differ.
- These bits must not be set when the ADCDC1 bit is set in PWR_CR
register.
28 27 26 25
12 11 10 9
EXTI2[3:0]
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These bits are written by software to select the source input for the EXTIx
external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
1001: PJ[x] pin
1010: PK[x] pin
DocID018909 Rev 11
System configuration controller (SYSCFG)
24 23 22 21
Reserved
8 7 6 5
EXTI1[3:0]
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20 19 18 17
4 3 2 1
EXTI0[3:0]
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16
0
rw
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