Dma2D Interrupt Status Register (Dma2D_Isr) - STMicroelectronics STM32F405 Reference Manual

Chrom-Art Accelerator™ controller (DMA2D)
11.5.2

DMA2D Interrupt Status Register (DMA2D_ISR)

Address offset: 0x0004
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:6 Reserved, must be kept at reset value
Bit 5 CEIF: Configuration error interrupt flag
Bit 4 CTCIF: CLUT transfer complete interrupt flag
Bit 3 CAEIF: CLUT access error interrupt flag
Bit 2 TWIF: Transfer watermark interrupt flag
Bit 1 TCIF: Transfer complete interrupt flag
Bit 0 TEIF: Transfer error interrupt flag
356/1731
27 26 25 24
11 10 9 8
Reserved
This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or
DMA2D_BGPFCCR is set and a wrong configuration has been programmed.
This bit is set when the CLUT copy from a system memory area to the internal DMA2D
memory is complete.
This bit is set when the CPU accesses the CLUT while the CLUT is being automatically
copied from a system memory to the internal DMA2D.
This bit is set when the last pixel of the watermarked line has been transferred.
This bit is set when a DMA2D transfer operation is complete (data transfer only).
This bit is set when an error occurs during a DMA transfer (data transfer or automatic
CLUT loading).
DocID018909 Rev 11
23 22 21
Reserved
7 6 5
CEIF
r
20 19 18
4 3 2
CTCIF CAEIF TWIF TCIF
r r r
RM0090
17 16
1 0
TEIF
r r