Figure 95. Counter Timing Diagram, Internal Clock Divided By 1; Figure 96. Counter Timing Diagram, Internal Clock Divided By 2; Figure 97. Counter Timing Diagram, Internal Clock Divided By 4 - STMicroelectronics STM32F405 Reference Manual

Advanced-control timers (TIM1&TIM8)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
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Figure 95. Counter timing diagram, internal clock divided by 1

CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow (cnt_udf)
Update event (UEV)
Update interrupt flag (UIF)

Figure 96. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 97. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
DocID018909 Rev 11
05 04 03 02 01 00 36 35 34 33 32 31 30 2F
0002 0001 0000 0036 0035 0034 0033
0001 0000
RM0090
0036 0035