Table 145. Frame Formats; Figure 304. Mute Mode Using Address Mark Detection; Parity Control - STMicroelectronics STM32F405 Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
In this example, the current address of the receiver is 1
(programmed in the USART_CR2 register)
RX
RWU
RWU written to 1
(RXNE was cleared)
30.3.7

Parity control

Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame
length defined by the M bit, the possible USART frame formats are as listed in
M bit
1. Legends: SB: start bit, STB: stop bit, PB: parity bit.
Even parity
The parity bit is calculated to obtain an even number of "1s" inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
E.g.: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit in
USART_CR1 = 0).
Odd parity
The parity bit is calculated to obtain an odd number of "1s" inside the frame made of the 7 or
8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
E.g.: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit in
USART_CR1 = 1).
Parity checking in reception
If the parity check fails, the PE flag is set in the USART_SR register and an interrupt is
generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by a software
sequence (a read from the status register followed by a read or write access to the
USART_DR data register).
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Figure 304. Mute mode using address mark detection

IDLE Addr=0 Data 1
nonmatching address
PCE bit
0 0
0 1
1 0
1 1
DocID018909 Rev 11
Data 2 IDLE Addr=1
Mute Mode
Matching address

Table 145. Frame formats

| SB | 7-bit data | PB | STB |
RXNE
RXNE RXNE
Data 3 Data 4 Addr=2
Normal Mode
nonmatching address
(1)
USART frame
| SB | 8 bit data | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
RM0090
Data 5
Mute Mode
Table 145.