Lsi Clock; System Clock (Sysclk) Selection; Clock Security System (Css) - STMicroelectronics STM32F405 Reference Manual

Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
The LSERDY flag in the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the
interrupt register
External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the
domain control register
with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be
left HI-Z. See
7.2.5

LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The
clock frequency is around 32 kHz. For more details, refer to the electrical characteristics
section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the
status register
The LSIRDY flag in the
speed internal oscillator is stable or not. At startup, the clock is not released until this bit is
set by hardware. An interrupt can be generated if enabled in the
(RCC_CIR).
7.2.6

System clock (SYSCLK) selection

After a system reset, the HSI oscillator is selected as the system clock. When a clock source
is used directly or through PLL as the system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is
selected, the switch occurs when the clock source is ready. Status bits in the
control register (RCC_CR)
used as the system clock.
7.2.7

Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock
failure event is sent to the break inputs of advanced-control timers TIM1 and TIM8, and an
interrupt is generated to inform the software about the failure (clock security system
interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the
®
Cortex -M4 with FPU NMI (non-maskable interrupt) exception vector.
Note: When the CSS is enabled, if the HSE clock happens to fail, the CSS generates an interrupt,
which causes the automatic generation of an NMI. The NMI is executed indefinitely unless
the CSS interrupt pending bit is cleared. As a consequence, the application has to clear the
CSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register
(RCC_CIR).
220/1731
RCC Backup domain control register (RCC_BDCR)
(RCC_CIR).
(RCC_BDCR). The external clock signal (square, sinus or triangle)
Figure 22.
(RCC_CSR).
RCC clock control & status register (RCC_CSR)
indicate which clock(s) is (are) ready and which clock is currently
DocID018909 Rev 11
RM0090
indicates if the
RCC clock
RCC Backup
RCC clock control &
indicates if the low-
RCC clock interrupt register
RCC clock