Gpio Port Input Data Register (Gpiox_Idr) (X = A; Gpio Port Output Data Register (Gpiox_Odr) (X = A - STMicroelectronics STM32F405 Reference Manual

RM0090
Bits 2y:2y+1 PUPDRy[1:0]: Port x configuration bits (y = 0..15)
8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..I/J/K)
Address offset: 0x10
Reset value: 0x0000 XXXX (where X means undefined)
31 30 29 28
15 14 13 12
IDR15 IDR14 IDR13 IDR12
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDRy: Port input data (y = 0..15)
8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..I/J/K)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
15 14 13
ODR15 ODR14 ODR13 ODR12 ODR11 ODR10
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODRy: Port output data (y = 0..15)
Note: For atomic bit set/reset, the ODR bits can be individually set and reset by writing to the
These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
27 26 25
11 10 9
IDR11 IDR10 IDR9
r r r r
These bits are read-only and can be accessed in word mode only. They contain the input
value of the corresponding I/O port.
28 27 26 25
12 11 10 9
ODR9
rw rw rw rw
These bits can be read and written by software.
GPIOx_BSRR register (x = A..I/J/K).
DocID018909 Rev 11
24 23 22 21
Reserved
8 7 6 5
IDR8 IDR7 IDR6 IDR5
r r r
24 23 22
Reserved
8 7 6
ODR8 ODR7 ODR6 ODR5
rw rw rw
General-purpose I/Os (GPIO)
20 19 18
4 3 2
IDR4 IDR3 IDR2
r r r r
21 20 19 18
5 4 3 2
ODR4 ODR3 ODR2
rw rw rw rw
17 16
1 0
IDR1 IDR0
r r
17 16
1 0
ODR1 ODR0
rw rw
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