Figure 412. Interrupt Hierarchy; Otg_Hs Control And Status Registers - STMicroelectronics STM32F405 Reference Manual

RM0090
31 30 29 28 27 26 25 24 23 22 21 20 19 18
Core interrupt
(1)
register
Interrupt
sources
Host port control and status
Host all channels interrupt
Host channels interrupt
registers 0 to 11
1. The core interrupt register bits are shown in
page 1404.
35.12

OTG_HS control and status registers

By reading from and writing to the control and status registers (CSRs) through the AHB
slave interface, the application controls the OTG_HS controller. These registers are 32 bits

Figure 412. Interrupt hierarchy

17:10 9 8
Device all endpoints
interrupt register
21:16 5:0
OUT endpoints IN endpoints
Device IN/OUT endpoint
interrupt registers 0 to 5
register
register
DocID018909 Rev 11
USB on-the-go high-speed (OTG_HS)
AND
7:3 2 1 0
Core interrupt mask
OTG
interrupt
register
Device all endpoints
interrupt mask register
Device IN/OUT
Device each IN/OUT endpoint
endpoints common
interrupt mask register
interrupt mask register
Host all channels
interrupt mask register
Host channels interrupt
mask registers 0 to 11
OTG_HS core interrupt register (OTG_HS_GINTSTS) on
Interrupt
AND
OR
Global interrupt
mask (Bit 0)
AHB configuration
register
register
Device each endpoint
interrupt register
31:16 15:0
EP1OUT EP1IN
OR
endp_multi_proc_intrpt
endp_interrupt[31:0]
Device each endpoint
interrupt mask register
ai16093b
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