Dma2D Interrupt Flag Clear Register (Dma2D_Ifcr) - STMicroelectronics STM32F405 Reference Manual

RM0090
11.5.3

DMA2D interrupt flag clear register (DMA2D_IFCR)

Address offset: 0x0008
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:6 Reserved, must be kept at reset value
Bit 5 CCEIF: Clear configuration error interrupt flag
Bit 4 CCTCIF: Clear CLUT transfer complete interrupt flag
Bit 3 CAECIF: Clear CLUT access error interrupt flag
Bit 2 CTWIF: Clear transfer watermark interrupt flag
Bit 1 CTCIF: Clear transfer complete interrupt flag
Bit 0 CTEIF: Clear Transfer error interrupt flag
27 26 25 24
11 10 9 8
Reserved
Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register
Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register
Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register
Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register
Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register
Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register
DocID018909 Rev 11
Chrom-Art Accelerator™ controller (DMA2D)
23 22 21
Reserved
7 6 5
CCEIF
rc_w1
20 19 18
4 3 2
CCTCIF CAECIF CTWIF
rc_w1 rc_w1 rc_w1
17 16
1 0
CTCIF CTEIF
rc_w1 rc_w1
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