Figure 357. Rmii Clock Sources; Figure 358. Clock Scheme; Mii/Rmii Selection - STMicroelectronics STM32F405 Reference Manual

Ethernet (ETH): media access control (MAC) with DMA controller
RMII clock sources
Either clock the PHY from an external 50 MHz clock or use a PHY with an embedded PLL to
generate the 50 MHz frequency.
33.4.4

MII/RMII selection

The mode, MII or RMII, is selected using the configuration bit 23, MII_RMII_SEL, in the
SYSCFG_PMC register. The application has to set the MII/RMII mode while the Ethernet
controller is under reset or before enabling the clocks.
MII/RMII internal clock scheme
The clock scheme required to support both the MII and RMII, as well as 10 and 100 Mbit/s
operations is described in
MII_TX_CLK as AF
(25 MHz or 2.5 MHz)
MII_RX_CLK as AF
(25 MHz or 2.5 MHz)
RMII_REF_CK as AF
(50 MHz)
1. The MII/RMII selection is controlled through bit 23, MII_RMII_SEL, in the SYSCFG_PMC register.
To save a pin, the two input clock signals, RMII_REF_CK and MII_RX_CLK, are multiplexed
on the same GPIO pin.
1124/1731

Figure 357. RMII clock sources

Figure 358.

Figure 358. Clock scheme

25 MHz or 2.5 MHz
GPIO and AF
controller
Sync. divider
50 MHz
/2 for 100 Mb/s
/20 for 10 Mb/s
25 MHz or 2.5 MHz
GPIO and AF
controller
DocID018909 Rev 11
0 25 MHz MACTXCLK
1 or 2.5 MHz
0 MII
(1)
1 RMII
25 MHz
0 MACRXCLK
or 2.5 MHz
1
HCLK
HCLK
must be greater
than 25 MHz
RM0090
MAC
TX
AHB
RX
RMII
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