Table 44. Source And Destination Address; Dma Streams - STMicroelectronics STM32F405 Reference Manual

RM0090
10.3.5

DMA streams

Each of the 8 DMA controller streams provides a unidirectional transfer link between a
source and a destination.
Each stream can be configured to perform:
•
Regular type transactions: memory-to-peripherals, peripherals-to-memory or memory-
to-memory transfers
•
Double-buffer type transactions: double buffer transfers using two memory pointers for
the memory (while the DMA is reading/writing from/to a buffer, the application can
write/read to/from the other buffer).
The amount of data to be transferred (up to 65535) is programmable and related to the
source width of the peripheral that requests the DMA transfer connected to the peripheral
AHB port. The register that contains the amount of data items to be transferred is
decremented after each transaction.
10.3.6 Source, destination and transfer modes
Both source and destination transfers can address peripherals and memories in the entire
4 GB area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF.
The direction is configured using the DIR[1:0] bits in the DMA_SxCR register and offers
three possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory
transfers.
Bits DIR[1:0] of the
DMA_SxCR register
00
01
10
11
When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register)
is a half-word or a word, respectively, the peripheral or memory address written into the
DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word
address boundary, respectively.
Peripheral-to-memory mode
Figure 36
When this mode is enabled (by setting the bit EN in the DMA_SxCR register), each time a
peripheral request occurs, the stream initiates a transfer from the source to fill the FIFO.
When the threshold level of the FIFO is reached, the contents of the FIFO are drained and
stored into the destination.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral
requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in
the DMA_SxCR register is cleared by software.
Table 44 describes the corresponding source and destination addresses.

Table 44. Source and destination address

Direction
Peripheral-to-memory
Memory-to-peripheral
Memory-to-memory
reserved
describes this mode.
DocID018909 Rev 11
DMA controller (DMA)
Source address Destination address
DMA_SxPAR DMA_SxM0AR
DMA_SxM0AR DMA_SxPAR
DMA_SxPAR DMA_SxM0AR
- -
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