Rcc Ahb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb1Lpenr) - STMicroelectronics STM32F405 Reference Manual

Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
7.3.16 RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR)
Address offset: 0x50
Reset value: 0x7E67 91FF
Access: no wait state, word, half-word and byte access.
31 30 29
OTGHS OTGH ETHPT
S
ULPILPE
Reser
N LPEN LPEN
-ved
rw rw
15 14 13
FLITF
LPEN LPEN
Reserved
rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 OTGHSULPILPEN: USB OTG HS ULPI clock enable during Sleep mode
Bit 29 OTGHSLPEN: USB OTG HS clock enable during Sleep mode
Bit 28 ETHMACPTPLPEN: Ethernet PTP clock enable during Sleep mode
Bit 27 ETHMACRXLPEN: Ethernet reception clock enable during Sleep mode
Bit 26 ETHMACTXLPEN: Ethernet transmission clock enable during Sleep mode
Bit 25 ETHMACLPEN: Ethernet MAC clock enable during Sleep mode
Bits 24:23 Reserved, must be kept at reset value.
Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode
252/1731
28 27 26 25
ETHMA
ETHRX ETHTX
P
LPEN LPEN
LPEN
rw rw rw rw
12 11 10
CRC
Reserved
rw
Set and cleared by software.
0: USB OTG HS ULPI clock disabled during Sleep mode
1: USB OTG HS ULPI clock enabled during Sleep mode
Set and cleared by software.
0: USB OTG HS clock disabled during Sleep mode
1: USB OTG HS clock enabled during Sleep mode
Set and cleared by software.
0: Ethernet PTP clock disabled during Sleep mode
1: Ethernet PTP clock enabled during Sleep mode
Set and cleared by software.
0: Ethernet reception clock disabled during Sleep mode
1: Ethernet reception clock enabled during Sleep mode
Set and cleared by software.
0: Ethernet transmission clock disabled during sleep mode
1: Ethernet transmission clock enabled during sleep mode
Set and cleared by software.
0: Ethernet MAC clock disabled during Sleep mode
1: Ethernet MAC clock enabled during Sleep mode
Set and cleared by software.
0: DMA2 clock disabled during Sleep mode
1: DMA2 clock enabled during Sleep mode
DocID018909 Rev 11
24 23 22
DMA2
C
LPEN
Reserved
rw
9 8 7 6
GPIOG
GPIOI GPIOH
G
LPEN LPEN
LPEN
rw rw rw
21 20 19 18
BKPSRA
DMA1
M
LPEN
Reserved
LPEN
rw rw
5 4 3 2
GPIO
GPIOE GPIOD GPIOC
F
LPEN LPEN LPEN
LPEN
rw rw rw rw
RM0090
17 16
SRAM SRAM
2 1
LPEN LPEN
rw rw
1 0
GPIOB GPIOA
LPEN LPEN
rw rw