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Flexible static memory controller (FSMC)
36.6.2
NAND Flash / PC Card supported memories and transactions
Table 245
Transactions not allowed (or not supported) by the NAND Flash / PC Card controller appear
in gray.
Device
NAND 8-bit
NAND 16-bit
36.6.3
Timing diagrams for NAND and PC Card
Each PC Card/CompactFlash and NAND Flash memory bank is managed through a set of
registers:
•
Control register: FSMC_PCRx
•
Interrupt status register: FSMC_SRx
•
ECC register: FSMC_ECCRx
•
Timing register for Common memory space: FSMC_PMEMx
•
Timing register for Attribute memory space: FSMC_PATTx
•
Timing register for I/O space: FSMC_PIOx
Each timing configuration register contains three parameters used to define number of
HCLK cycles for the three phases of any PC Card/CompactFlash or NAND Flash access,
plus one parameter that defines the timing for starting driving the databus in the case of a
write.
Figure 452
knowing that Attribute and I/O (only for PC Card) memory space access timings are similar.
1574/1731
below shows the supported devices, access modes and transactions.
Table 245. Supported memories and transactions
Mode
R/W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
shows the timing parameter definitions for common memory accesses,
DocID018909 Rev 11
AHB
Memory
data size
data size
not allowed
8
8
Y
8
8
Y
16
8
Y
16
8
Y
32
8
Y
32
8
Y
8
16
Y
8
16
N
16
16
Y
16
16
Y
32
16
Y
32
16
Y
Allowed/
Comments
Split into 2 FSMC accesses
Split into 2 FSMC accesses
Split into 4 FSMC accesses
Split into 4 FSMC accesses
Split into 2 FSMC accesses
Split into 2 FSMC accesses
RM0090
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