Dma Interrupts - STMicroelectronics STM32F405 Reference Manual

RM0090
31 30 29 28 27 26 25
rw rw rw rw rw rw rw
.
Bits 31:0 RTSL: Receive frame time stamp low
The DMA updates this field with the 32 least significant bits of the time stamp captured for the
corresponding receive frame. The DMA updates this field only for the last descriptor of the receive
frame indicated by last descriptor status bit (RDES0[8]). When this field and the RTSH field in
RDES7 show all ones, the time stamp must be treated as corrupt.
•
RDES7: Receive descriptor Word7
The table below describes the fields that have a different meaning for RDES7 when the
receive descriptor is closed and time stamping is enabled.
31 30 29 28 27 26 25
rw rw rw rw rw rw rw
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Bits 31:0 RTSH: Receive frame time stamp high
33.6.9

DMA interrupts

Interrupts can be generated as a result of various events. The ETH_DMASR register
contains all the bits that might cause an interrupt. The ETH_DMAIER register contains an
enable bit for each of the events that can cause an interrupt.
There are two groups of interrupts, Normal and Abnormal, as described in the ETH_DMASR
register. Interrupts are cleared by writing a 1 to the corresponding bit position. When all the
enabled interrupts within a group are cleared, the corresponding summary bit is cleared. If
the MAC core is the cause for assertion of the interrupt, then any of the TSTS or PMTS bits
in the ETH_DMASR register is set high.
Interrupts are not queued and if the interrupt event occurs before the driver has responded
to it, no additional interrupts are generated. For example, the Receive Interrupt bit
(ETH_DMASR register [6]) indicates that one or more frames were transferred to the
STM32F4xx buffer. The driver must scan all descriptors, from the last recorded position to
the first one owned by the DMA.
An interrupt is generated only once for simultaneous, multiple events. The driver must scan
the ETH_DMASR register for the cause of the interrupt. The interrupt is not generated again
unless a new interrupting event occurs, after the driver has cleared the appropriate bit in the
ETH_DMASR register. For example, the controller generates a Receive interrupt
(ETH_DMASR register[6]) and the driver begins reading the ETH_DMASR register. Next,
receive buffer unavailable (ETH_DMASR register[7]) occurs. The driver clears the Receive
interrupt. Even then, a new interrupt is generated, due to the active or pending Receive
buffer unavailable interrupt.
Ethernet (ETH): media access control (MAC) with DMA controller
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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The DMA updates this field with the 32 most significant bits of the time stamp captured for the
corresponding receive frame. The DMA updates this field only for the last descriptor of the receive
frame indicated by last descriptor status bit (RDES0[8]).
When this field and RDES7's RTSL field show all ones, the time stamp must be treated as
corrupt.
DocID018909 Rev 11
RTSL
RTSH
9 8 7 6 5 4 3 2
9 8 7 6 5 4 3 2
1181/1731
1 0
1 0
1232