Mmc Register Description - STMicroelectronics STM32F405 Reference Manual

Ethernet (ETH): media access control (MAC) with DMA controller
33.8.2

MMC register description

Ethernet MMC control register (ETH_MMCCR)
Address offset: 0x0100
Reset value: 0x0000 0000
The Ethernet MMC Control register establishes the operating mode of the management
counters.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:6 Reserved, must be kept at reset value.
MCFHP: MMC counter Full-Half preset
Bit 5
MCP: MMC counter preset
Bit 4
counter becoming half-full or full.
Bit 3 MCF: MMC counter freeze
Bit 2 ROR: Reset on read
Bit 1 CSR: Counter stop rollover
Bit 0 CR: Counter reset
Ethernet MMC receive interrupt register (ETH_MMCRIR)
Address offset: 0x0104
Reset value: 0x0000 0000
The Ethernet MMC receive interrupt register maintains the interrupts generated when
receive statistic counters reach half their maximum values. (MSB of the counter is set.) It is
a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that
1202/1731
Reserved
When MCFHP is low and bit4 is set, all MMC counters get preset to almost-half value. All
frame-counters get preset to 0x7FFF_FFF0 (half - 16)
When MCFHP is high and bit4 is set, all MMC counters get preset to almost-full value. All
frame-counters get preset to 0xFFFF_FFF0 (full - 16)
When set, all counters will be initialized or preset to almost full or almost half as per
Bit5 above. This bit will be cleared automatically after 1 clock cycle. This bit along
with bit5 is useful for debugging and testing the assertion of interrupts due to MMC
When set, this bit freezes all the MMC counters to their current value. (None of the MMC
counters are updated due to any transmitted or received frame until this bit is cleared to 0. If
any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in
this mode.)
When this bit is set, the MMC counters is reset to zero after read (self-clearing after reset).
The counters are cleared when the least significant byte lane (bits [7:0]) is read.
When this bit is set, the counter does not roll over to zero after it reaches the maximum
value.
When it is set, all counters are reset. This bit is cleared automatically after 1 clock cycle.
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