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RM0090
Table 210. OTG_HS register map and reset values (continued)
Offset
Register
OTG_HS_DO
EPTSIZ2
0xB50
Reset value
OTG_HS_DO
EPDMA2
0xB54
Reset value
0
OTG_HS_DO
EPDMAB2
0xB5C
Reset value
0
OTG_HS_DO
EPTSIZ3
0xB70
Reset value
OTG_HS_DO
EPDMA3
0xB74
Reset value
0
OTG_HS_DO
EPDMAB3
0xB7C
Reset value
0
OTG_HS_PC
GCCTL
0xE00
Reset value
Refer to Section: Memory map for the register boundary addresses.
35.13
OTG_HS programming model
35.13.1
Core initialization
The application must perform the core initialization sequence. If the cable is connected
during power-up, the current mode of operation bit in the Core interrupt register (CMOD bit
in OTG_HS_GINTSTS) reflects the mode. The OTG_HS controller enters host mode when
an "A" plug is connected or peripheral mode when a "B" plug is connected.
This section explains the initialization of the OTG_HS controller after power-on. The
application must follow the initialization sequence irrespective of host or peripheral mode
operation. All core global registers are initialized according to the core's configuration:
PKTCNT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PKTCNT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DocID018909 Rev 11
USB on-the-go high-speed (OTG_HS)
0
0
0
0
0
0
0
0
0
DMAADDR
0
0
0
0
0
0
0
0
0
DMABADDR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMAADDR
0
0
0
0
0
0
0
0
0
DMABADDR
0
0
0
0
0
0
0
0
0
Reserved
XFRSIZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XFRSIZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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