Dma2D Output Memory Address Register (Dma2D_Omar) - STMicroelectronics STM32F405 Reference Manual

Chrom-Art Accelerator™ controller (DMA2D)
11.5.16

DMA2D output memory address register (DMA2D_OMAR)

Address offset: 0x003C
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31: 0 MA[31: 0]: Memory Address
368/1731
27 26 25 24
rw rw rw rw
11 10 9 8
rw rw rw rw
Address of the data used for the output FIFO. These bits can only be written when data
transfers are disabled. Once the transfer has started, they are read-only.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned.
DocID018909 Rev 11
23 22 21
MA[31:16]
rw rw rw
7 6 5
MA[15:0]
rw rw rw
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
RM0090
16
rw
0
rw