Figure 281. Audio Sampling Frequency Definition; Figure 282. I; Clock Generator - STMicroelectronics STM32F405 Reference Manual

RM0090
28.4.4

Clock generator

2
The I S bitrate determines the dataflow on the I
frequency.
2
I S bitrate = number of bits per channel × number of channels × sampling audio frequency
For a 16-bit audio, left and right channel, the I
2
I S bitrate = 16 × 2 × F
It will be: I
When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
I2SxCLK
1. Where x could be 2 or 3.
Figure 281
performance, the I2SxCLK clock source can be either the PLLI2S output (through R division
factor) or an external clock (mapped to I2S_CKIN pin).
The audio sampling frequency can be 192 kHz, 96 kHz, or 48 kHz. In order to reach the
desired frequency, the linear divider needs to be programmed according to the formulas
below:
When the master clock is generated (MCKOE in the SPI_I2SPR register is set):
F = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
S
F = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
S
S
2
S bitrate = 32 x 2 x F

Figure 281. Audio sampling frequency definition

16-bit or 32-bit Left channel
sampling point
F : Audio sampling frequency
S

Figure 282. I

8-bit Linear
Divider +
reshaping stage
I2SDIV[7:0]
MCKOE ODD
presents the communication clock architecture. To achieve high-quality audio
DocID018909 Rev 11
2
S data line and the I
2
S bitrate is calculated as follows:
if the packet length is 32-bit wide.
S
16-bit or 32-bit Right channel
32-bits or 64-bits
F
S
2
S clock generator architecture
Divider by 4
I2SMOD
Serial peripheral interface (SPI)
2
S clock signal
sampling point
0
0
Div2
1
1
MCKOE
CHLEN
MCK
CK
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