Table 284. Programmable Nand Flash/Pc Card Access Parameters; Table 285. 8-Bit Nand Flash; External Memory Interface Signals - STMicroelectronics STM32F405 Reference Manual

RM0090
Parameter
Memory setup
time
Memory wait
Memory hold
Memory
databus high-Z
37.6.1

External memory interface signals

The following tables list the signals that are typically used to interface NAND Flash memory
and PC Card.
Note: The prefix "N" identifies the signals which are active low.
8-bit NAND Flash memory
t
FMC signal name
NOE(= NRE)
NWAIT/INT[3:2]
Theoretically, there is no capacity limitation as the FMC can manage as many address
cycles as needed.

Table 284. Programmable NAND Flash/PC Card access parameters

Function
Number of clock cycles (HCLK)
required to set up the address
before the command assertion
Minimum duration (in HCLK clock
cycles) of the command assertion
Number of clock cycles (HCLK)
during which the address must be
held (as well as the data if a write
access is performed) after the
command de-assertion
Number of clock cycles (HCLK)
during which the data bus is kept
in high-Z state after a write
access has started

Table 285. 8-bit NAND Flash

I/O
A[17] O
A[16] O
D[7:0] I/O
NCE[x] O
O
NWE O
I
DocID018909 Rev 11
Access mode
Read/Write
Read/Write
Read/Write
Write
NAND Flash address latch enable (ALE) signal
NAND Flash command latch enable (CLE) signal
8-bit multiplexed, bidirectional address/data bus
Chip Select, x = 2, 3
Output enable (memory signal name: read enable, NRE)
Write enable
NAND Flash ready/busy input signal to the FMC
Flexible memory controller (FMC)
Unit
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
Function
Min. Max.
1 256
2 255
1 254
1 255
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