Rng Control Register (Rng_Cr) - STMicroelectronics STM32F405 Reference Manual

Random number generator (RNG)
24.4.1

RNG control register (RNG_CR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
15 14 13
Bits 31:4 Reserved, must be kept at reset value
Bit 3 IE: Interrupt enable
Bit 2 RNGEN: Random number generator enable
Bits 1:0 Reserved, must be kept at reset value
24.4.2 RNG status register (RNG_SR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
15 14 13
Bits 31:3 Reserved, must be kept at reset value
Bit 6 SEIS: Seed error interrupt status
This bit is set at the same time as SECS, it is cleared by writing it to 0.
Bit 5 CEIS: Clock error interrupt status
This bit is set at the same time as CECS, it is cleared by writing it to 0.
Bits 4:3 Reserved, must be kept at reset value
760/1731
28 27 26 25
12 11 10 9
Reserved
0: RNG Interrupt is disabled
1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY=1 or SEIS=1 or
CEIS=1 in the RNG_SR register.
0: Random number generator is disabled
1: random Number Generator is enabled.
28 27 26 25
12 11 10 9
Reserved
0: No faulty sequence detected
1: One of the following faulty sequences has been detected:
– More than 64 consecutive bits at the same value (0 or 1)
– More than 32 consecutive alternances of 0 and 1 (0101010101...01)
An interrupt is pending if IE = 1 in the RNG_CR register.
0: The RNG_CLK clock was correctly detected
1: The RNG_CLK was not correctly detected (f
An interrupt is pending if IE = 1 in the RNG_CR register.
DocID018909 Rev 11
24 23 22 21
Reserved
8 7 6 5
24 23 22 21
Reserved
8 7 6 5
SEIS CEIS
rc_w0 rc_w0
RNG_CLK
20 19 18
4 3 2
IE RNGEN
rw rw
20 19 18
4 3 2
SECS CECS
Reserved
r
< f /16)
HCLK
RM0090
17 16
1 0
Reserved
17 16
1 0
DRDY
r r