Table 256. Sdram Address Mapping With 16-Bit Data Bus Width; Table 257. Sdram Address Mapping With 32-Bit Data Bus Width - STMicroelectronics STM32F405 Reference Manual

Flexible memory controller (FMC)
)

Table 256. SDRAM address mapping with 16-bit data bus width

Row size
Configuration
11-bit row size
configuration
Res.
Res.
Res.
12-bit row size
configuration
Res.
Res.
Res.
Res.
13-bit row size
configuration
Res.
Re Bank
s. [1:0]
1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to '0'.
2. Access to Reserved space (Res.) generates an AHB error.
3. BM0: is the byte mask for 16-bit access.

Table 257. SDRAM address mapping with 32-bit data bus width

Row size
configuration
11-bit row size
configuration
Res.
Res.
Res.
12-bit row size
configuration
Res.
Res.
1598/1731
Bank
Res.
[1:0]
Bank
Res.
[1:0]
Bank
[1:0]
Bank
[1:0]
Bank
Res.
[1:0]
Bank
[1:0]
Bank
[1:0]
Bank
[1:0]
Bank
[1:0]
Bank
[1:0]
Bank
[1:0]
Bank
Res.
[1:0]
Bank
Res.
[1:0]
Bank
[1:0]
Bank
[1:0]
Bank
Res.
[1:0]
Bank
[1:0]
Bank
[1:0]
Bank
Row[11:0]
[1:0]
HADDR(AHB address Lines)
Row[10:0]
Row[10:0]
Row[10:0]
Row[10:0]
Row[11:0]
Row[11:0]
Row[11:0]
Row[11:0]
Row[12:0]
Row[12:0]
Row[12:0]
Row[12:0]
HADDR(AHB address Lines)
Row[10:0]
Row[10:0]
Row[10:0]
Row[10:0]
Row[11:0]
Row[11:0]
Row[11:0]
DocID018909 Rev 11
RM0090
(1)(2)
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
(1)(2)
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
(3)
BM0
BM0
BM0
BM0
BM0
BM0
BM0
BM0
BM0
BM0
BM0
BM0
BM[1:0
(3)
]
BM[1:0
BM[1:0
BM[1:0
BM[1:0
BM[1:0
BM[1:0
BM[1:0