Rcc Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr) - STMicroelectronics STM32F405 Reference Manual

Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
Bit 2 GPIOCEN: IO port C clock enable
Bit 1 GPIOBEN: IO port B clock enable
Bit 0 GPIOAEN: IO port A clock enable
7.3.11

RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)

Address offset: 0x34
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
15 14 13
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSEN: USB OTG FS clock enable
Bit 6 RNGEN: Random number generator clock enable
Bit 5 HASHEN: Hash modules clock enable
244/1731
Set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
28 27 26 25
12 11 10 9
Reserved
Set and cleared by software.
0: USB OTG FS clock disabled
1: USB OTG FS clock enabled
Set and cleared by software.
0: Random number generator clock disabled
1: Random number generator clock enabled
Set and cleared by software.
0: Hash modules clock disabled
1: Hash modules clock enabled
DocID018909 Rev 11
24 23 22 21
Reserved
8 7 6 5
OTGFS RNG HASH
EN EN EN
rw rw rw
20 19 18 17
4 3 2 1
CRYP
EN
Reserved
rw
RM0090
16
0
DCMI
EN
rw