Rcc Registers; Rcc Clock Control Register (Rcc_Cr) - STMicroelectronics STM32F405 Reference Manual

RM0090
6.3

RCC registers

Refer to
register descriptions.
6.3.1

RCC clock control register (RCC_CR)

Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access
31 30 29
PLLSAI PLLSAI
RDY ON
Reserved
r
15 14 13
r r r
Bits 31:28 Reserved, must be kept at reset value.
Bit 29 PLLSAIRDY: PLLSAI clock ready flag
Bit 28 PLLSAION: PLLSAI enable
Bit 27 PLLI2SRDY: PLLI2S clock ready flag
Bit 26 PLLI2SON: PLLI2S enable
Bit 25 PLLRDY: Main PLL (PLL) clock ready flag
Bit 24 PLLON: Main PLL (PLL) enable
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
Section 1.1: List of abbreviations for registers
28 27 26 25
PLLI2S PLLI2S PLLRD
RDY ON Y
rw r rw r
12 11 10 9
HSICAL[7:0]
r r r r
Set by hardware to indicate that the PLLSAI is locked.
0: PLLSAI unlocked
1: PLLSAI locked
Set and cleared by software to enable PLLSAI.
Cleared by hardware when entering Stop or Standby mode.
0: PLLSAI OFF
1: PLLSAI ON
Set by hardware to indicate that the PLLI2S is locked.
0: PLLI2S unlocked
1: PLLI2S locked
Set and cleared by software to enable PLLI2S.
Cleared by hardware when entering Stop or Standby mode.
0: PLLI2S OFF
1: PLLI2S ON
Set by hardware to indicate that PLL is locked.
0: PLL unlocked
1: PLL locked
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit cannot be reset if PLL
clock is used as the system clock.
0: PLL OFF
1: PLL ON
DocID018909 Rev 11
for a list of abbreviations used in
24 23 22 21
PLLON
Reserved
rw
8 7 6
HSITRIM[4:0]
r rw rw rw
20 19 18
CSS HSE
ON BYP
rw rw
5 4 3 2
Res.
rw rw
17 16
HSE HSE
RDY ON
r rw
1 0
HSI
HSION
RDY
r rw
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