Secure digital input/output interface (SDIO)
31.3
SDIO functional description
The SDIO consists of two parts:
•
The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card
such as the clock generation unit, command and data transfer.
•
The APB2 interface accesses the SDIO adapter registers, and generates interrupt and
DMA request signals.
By default SDIO_D0 is used for data transfer. After initialization, the host can change the
databus width.
If a MultiMediaCard is connected to the bus, SDIO_D0, SDIO_D[3:0] or SDIO_D[7:0] can be
used for data transfer. MMC V3.31 or previous, supports only 1 bit of data so only SDIO_D0
can be used.
If an SD or SD I/O card is connected to the bus, data transfer can be configured by the host
to use SDIO_D0 or SDIO_D[3:0]. All data lines are operating in push-pull mode.
SDIO_CMD has two operational modes:
•
Open-drain for initialization (only for MMCV3.31 or previous)
•
Push-pull for command transfer (SD/SD I/O card MMC4.2 use push-pull drivers also for
initialization)
SDIO_CK is the clock to the card: one bit is transferred on both command and data lines
with each clock cycle. The clock frequency can vary between 0 MHz and 20 MHz (for a
MultiMediaCard V3.31), between 0 and 48 MHz for a MultiMediaCard V4.0/4.2, or between
0 and 25 MHz (for an SD/SD I/O card).
The SDIO uses two clock signals:
•
SDIO adapter clock (SDIOCLK = 48 MHz)
•
APB2 bus clock (PCLK2)
PCLK2 and SDIO_CK clock frequencies must respect the following condition:
The signals shown in
1014/1731
Figure 326. SDIO block diagram
(
) 3 8 ⁄
≥
Frequenc PCLK2
Table 149
are used on the MultiMediaCard/SD/SD I/O card bus.
DocID018909 Rev 11
×
(
Frequency SDIO_CK
RM0090
)
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