Table 275. Fmc_Bcrx Bit Fields; Figure 466. Moded Write Access Waveforms - STMicroelectronics STM32F405 Reference Manual

Advanced arm-based 32-bit mcus
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Flexible memory controller (FMC)
The differences with mode1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.
Bit No.
31-21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
1616/1731

Figure 466. ModeD write access waveforms

Table 275. FMC_BCRx bit fields

Bit name
Reserved
0x000
CCLKEN
As needed
CBURSTRW
0x0 (no effect in asynchronous mode)
CPSIZE
0x0 (no effect in asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep
ASYNCWAIT
at 0.
EXTMOD
0x1
WAITEN
0x0 (no effect in asynchronous mode)
WREN
As needed
WAITCFG
Don't care
WRAPMOD
0x0
WAITPOL
Meaningful only if bit 15 is 1
BURSTEN
0x0
Reserved
0x1
FACCEN
Set according to memory support
MWID
As needed
DocID018909 Rev 11
Value to set
RM0090

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