Table 264. Fmc_Bcrx Bit Fields; Table 265. Fmc_Btrx Bit Fields - STMicroelectronics STM32F405 Reference Manual

Flexible memory controller (FMC)
The one HCLK cycle at the end of the write transaction helps guarantee the address and
data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the
DATAST value must be greater than zero (DATAST > 0).
Bit
number
31-21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1
0
Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
1606/1731

Table 264. FMC_BCRx bit fields

Bit name
Reserved 0x000
CCLKEN As needed
CBURSTRW 0x0 (no effect in asynchronous mode)
CPSIZE 0x0 (no effect in asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at
ASYNCWAIT
0.
EXTMOD 0x0
WAITEN 0x0 (no effect in asynchronous mode)
WREN As needed
WAITCFG Don't care
WRAPMOD 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN Don't care
MWID As needed
MTYP[1:0] As needed, exclude 0x2 (NOR Flash memory)
MUXE 0x0
MBKEN 0x1

Table 265. FMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD Don't care
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+1 HCLK cycles for
DATAST
write accesses, DATAST HCLK cycles for read accesses).
DocID018909 Rev 11
Value to set
Value to set
RM0090