Rtc Shift Control Register (Rtc_Shiftr) - STMicroelectronics STM32F405 Reference Manual

Advanced arm-based 32-bit mcus

Table of Contents

Real-time clock (RTC)

RTC shift control register (RTC_SHIFTR)

Address offset: 0x2C

Backup domain reset value: 0x0000 0000

System reset: not affected

Bit 31 ADD1S: Add one second

0: No effect

1: Add one second to the clock/calendar

This bit is write only and is always read as zero. Writing to this bit has no effect when a shift

operation is pending (when SHPF=1, in RTC_ISR).

This function is intended to be used with SUBFS (see description below) in order to

effectively add a fraction of a second to the clock in an atomic operation.

Bits 30:15 Reserved

Bits 14:0 SUBFS: Subtract a fraction of a second

These bits are write only and is always read as zero. Writing to this bit has no effect when a

shift operation is pending (when SHPF=1, in RTC_ISR).

The value which is written to SUBFS is added to the synchronous prescaler's counter. Since

this counter counts down, this operation effectively subtracts from (delays) the clock by:

Delay (seconds) = SUBFS / ( PREDIV_S + 1 )

A fraction of a second can effectively be added to the clock (advancing the clock) when the

ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:

Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) .

Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be

This register is write protected. The write access procedure is described in

write protection on page 794

RTC time stamp time register (RTC_TSTR)

Address offset: 0x30

Backup domain reset value: 0x0000 0000

System reset: not affected

sure that the shadow registers have been updated with the shifted time.

Section 26.3.8: RTC

DocID018909 Rev 11

synchronization.

RTC register

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