Ltdc Interrupt Status Register (Ltdc_Isr) - STMicroelectronics STM32F405 Reference Manual

RM0090
16.7.9

LTDC Interrupt Status Register (LTDC_ISR)

This register returns the interrupt status flag
Address offset: 0x38
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:24 Reserved, must be kept at reset value
Bit 3 RRIF: Register Reload Interrupt Flag
Bit 2 TERRIF: Transfer Error interrupt flag
Bit 1 FUIF: FIFO Underrun Interrupt flag
Bit 0 LIF: Line Interrupt flag
16.7.10 LTDC Interrupt Clear Register (LTDC_ICR)
Address offset: 0x3C
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
27 26 25 24
11 10 9 8
Reserved
0: No Register Reload interrupt generated
1: Register Reload interrupt generated when a vertical blanking reload occurs (and the
first line after the active area is reached)
0: No Transfer Error interrupt generated
1: Transfer Error interrupt generated when a Bus error occurs
0: NO FIFO Underrun interrupt generated.
1: A FIFO underrun interrupt is generated, if one of the layer FIFOs is empty and pixel
data is read from the FIFO
0: No Line interrupt generated
1: A Line interrupt is generated, when a programmed line is reached
27 26 25 24
11 10 9 8
Reserved
DocID018909 Rev 11
23 22 21
Reserved
7 6 5
23 22 21
Reserved
7 6 5
LCD-TFT Controller (LTDC)
20 19 18 17
4 3 2
RRIF TERRIF FUIF
r r
20 19 18 17
4 3 2
CRRIF CTERRIF CFUIF
w w
16
1 0
LIF
r r
16
1 0
CLIF
w w
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