Figure 399. Bulk/Control In Transactions - STMicroelectronics STM32F405 Reference Manual

USB on-the-go full-speed (OTG_FS)
init _reg(ch_2)
set _ch_en
set _ch_en
set _ch_en
read_rx_sts
read_rx_fifo
set _ch_en
read_rx_stsre
read_rx_sts
read_rx_sts
De-allocate
The sequence of operations is as follows:
a)
b)
c)
d)
e)
1332/1731

Figure 399. Bulk/control IN transactions

Application
1
init_reg(ch _1)
1
write_tx_fifo
(ch_1)
2
(ch _2)
2
write_tx_fifo
(ch_1)
5
(ch _2)
(ch _2)
5
(ch _2)
7
De-allocate
(ch_1)
ad_rx_fifo
7
Disable
(ch _2) 9
11
(ch _2) 13
Initialize channel 2.
Set the CHENA bit in HCCHAR2 to write an IN request to the non-periodic request
queue.
The core attempts to send an IN token after completing the current OUT
transaction.
The core generates an RXFLVL interrupt as soon as the received packet is written
to the receive FIFO.
In response to the RXFLVL interrupt, mask the RXFLVL interrupt and read the
received packet status to determine the number of bytes received, then read the
receive FIFO accordingly. Following this, unmask the RXFLVL interrupt.
DocID018909 Rev 11
AHB Host
4
1
3
MPS
ch_1
1
ch_2
MPS
ch_1
ch_2
3
4
RXFLVL interrupt
1
ch_1
MPS
ch_2
ch_2
ch_2
6
RXFLVL interrupt
6
1
MPS
ch_2
8
RXFLVL interrupt
RXFLVL interrupt
10
CHH interrupt r
12
RM0090
USB Device
Non-Periodic Request
Queue
Assume that this queue
can hold 4 entries.
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