Table 301. Cortex - STMicroelectronics STM32F405 Reference Manual

Debug support (DBG)
Address
offset
0x00
0x04
0x0C
0x10
0x14
0x18
0x1C
0xF8
0xFC
Refer to the Cortex
1684/1731

Table 301. Cortex

Register name
AHB-AP Control and Status
Word
AHB-AP Transfer Address
AHB-AP Data Read/Write
AHB-AP Banked Data 0
AHB-AP Banked Data 1
AHB-AP Banked Data 2
AHB-AP Banked Data 3
AHB-AP Debug ROM Address Base Address of the debug interface
AHB-AP ID Register
®
-M4 with FPU r0p1 TRM for further details.
DocID018909 Rev 11
®
-M4 with FPU AHB-AP registers
Configures and controls transfers through the AHB
interface (size, hprot, status on current transfer, address
increment type
Directly maps the 4 aligned data words without rewriting
the Transfer Address Register.
RM0090
Notes
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-
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