Tim9/12 Capture/Compare Register 1 (Timx_Ccr1) - STMicroelectronics STM32F405 Reference Manual

General-purpose timers (TIM9 to TIM14)
19.4.11

TIM9/12 capture/compare register 1 (TIMx_CCR1)

Address offset: 0x34
Reset value: 0x0000
15 14 13
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Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
19.4.12 TIM9/12 capture/compare register 2 (TIMx_CCR2)
Address offset: 0x38
Reset value: 0x0000
15 14 13
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Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
674/1731
12 11 10 9
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If channel CC1 is configured as output:
CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(OC1PE bit). Else the preload value is copied into the active capture/compare 1 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the TIMx_CNT
counter and signaled on the OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
12 11 10 9
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If channel CC2 is configured as output:
CCR2 is the value to be loaded into the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(OC2PE bit). Else the preload value is copied into the active capture/compare 2 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the TIMx_CNT
counter and signalled on the OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
DocID018909 Rev 11
8 7 6 5
CCR1[15:0]
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8 7 6 5
CCR2[15:0]
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4 3 2 1
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4 3 2 1
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RM0090
0
rw
0
rw