Figure 447. Asynchronous Wait During A Read Access - STMicroelectronics STM32F405 Reference Manual

Flexible static memory controller (FSMC)
1. DATAST in FSMC_BTRx register) Memory asserts the WAIT signal aligned to
NOE/NWE which toggles:
2. Memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
then
DATAST
otherwise
where max_wait_assertion_time is the maximum time taken by the memory to assert
the WAIT signal once NEx/NOE/NWE is low.
Figure 447
memory access after WAIT is released by the asynchronous memory (independently of the
above cases).
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
1556/1731
≥ (
DATAST 4
max_wait_assertion_time
(
≥ ( × )
4 HCLK max_wait_assertion_time
+
and Figure 448 show the number of HCLK clock cycles that are added to the

Figure 447. Asynchronous wait during a read access

DocID018909 Rev 11
× )
HCLK + max_wait_assertion_time
>
address_phase
–
≥ ×
DATAST 4 HCLK
+ hold_phase
–
address_phase hold_phase
RM0090
)