Table 220. Nor Flash/Psram Controller: Example Of Supported Memories; And Transactions; Supported Memories And Transactions - STMicroelectronics STM32F405 Reference Manual

Flexible static memory controller (FSMC)
FSMC signal name
AD[15:0]
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1]
NBL[0]
PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26
address lines).
36.5.2

Supported memories and transactions

Table 220
transactions when the memory data bus is 16-bit for NOR, PSRAM and SRAM.
Transactions not allowed (or not supported) by the FSMC in this example appear in gray.

Table 220. NOR Flash/PSRAM controller: example of supported memories

Device
NOR Flash
(muxed I/Os
and nonmuxed
I/Os)
1538/1731
Table 219. Multiplexed I/O PSRAM (continued)
I/O
I/O 16-bit multiplexed, bidirectional address/data bus
O Chip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
O Output enable
O Write enable
O Address valid PSRAM input (memory signal name: NADV)
I PSRAM wait input signal to the FSMC
O Upper byte enable (memory signal name: NUB)
O Lowed byte enable (memory signal name: NLB)
below displays an example of the supported devices, access modes and
Mode R/W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous
R
page
Synchronous R
Synchronous R
Synchronous R
DocID018909 Rev 11
Function

and transactions

AHB Allowed/
Memory
data
data size
size allowed
8 16
8 16
16 16
16 16
32 16
32 16
- 16
8 16
16 16
32 16
not Comments
Y
N
Y
Y
Y Split into 2 FSMC accesses
Y Split into 2 FSMC accesses
N Mode is not supported
N
Y
Y
RM0090