Table 195. Core Global Control And Status Registers (Csrs); Figure 395. Csr Memory Map - STMicroelectronics STM32F405 Reference Manual

RM0090
34.16.1 CSR memory map
The host and device mode registers occupy different addresses. All registers are
implemented in the AHB clock domain.
1. x = 3 in device mode and x = 7 in host mode.
Global CSR map
These registers are available in both host and device modes.

Table 195. Core global control and status registers (CSRs)

Acronym
OTG_FS_GOTGCTL
OTG_FS_GOTGINT
OTG_FS_GAHBCFG
OTG_FS_GUSBCFG
OTG_FS_GRSTCTL

Figure 395. CSR memory map

0000h
0400h
0800h
Device mode CSRs (1.5 Kbyte)
0E00h
Power and clock gating CSRs (0.5 Kbyte)
1000h
Device EP 0/Host channel 0 FIFO (4 Kbyte)
2000h
Device EP1/Host channel 1 FIFO (4 Kbyte)
3000h
Device EP (x – 1)
Device EP x
2 0000h
Direct access to data FIFO RAM
for debugging (128 Kbyte)
3 FFFFh
Address
offset
0x000 OTG_FS control and status register (OTG_FS_GOTGCTL) on page 1262
0x004 OTG_FS interrupt register (OTG_FS_GOTGINT) on page 1264
0x008 OTG_FS AHB configuration register (OTG_FS_GAHBCFG) on page 1265
0x00C OTG_FS USB configuration register (OTG_FS_GUSBCFG) on page 1266
0x010 OTG_FS reset register (OTG_FS_GRSTCTL) on page 1268
DocID018909 Rev 11
USB on-the-go full-speed (OTG_FS)
Core global CSRs (1 Kbyte)
Host mode CSRs (1 Kbyte)
(1) (1)
/Host channel (x – 1)
(1) (1)
/Host channel x FIFO (4 Kbyte)
Reserved
Register name
DFIFO
push/pop
to this region
FIFO (4 Kbyte)
DFIFO
debug read/
write to this
region
ai15615b
1257/1731
1368