Table 280. Fmc_Bcrx Bit Fields; Table 281. Fmc_Btrx Bit Fields - STMicroelectronics STM32F405 Reference Manual

Flexible memory controller (FMC)
they are held low.
Bit No.
31-21
20
19
18-16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1
0
Bit No.
31:30
29:28
27-24
27-24
23-20
19-16
15-8
7-4
3-0
1624/1731

Table 280. FMC_BCRx bit fields

Bit name
Reserved 0x000
CCLKEN As needed
CBURSTRW No effect on synchronous read
CPSIZE As needed (0x1 for CRAM 1.5)
ASYNCWAIT 0x0
EXTMOD 0x0
to be set to 1 if the memory supports this feature, to be kept at 0
WAITEN
otherwise
WREN no effect on synchronous read
WAITCFG to be set according to memory
WRAPMOD 0x0
WAITPOL to be set according to memory
BURSTEN 0x1
Reserved 0x1
FACCEN Set according to memory support (NOR Flash memory)
MWID As needed
MTYP[1:0] 0x1 or 0x2
MUXEN As needed
MBKEN 0x1

Table 281. FMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Data latency
DATLAT Data latency
0x0 to get CLK = HCLK (Not supported)
CLKDIV 0x1 to get CLK = 2 × HCLK
..
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
DATAST Don't care
ADDHLD Don't care
ADDSET[3:0] Don't care
DocID018909 Rev 11
Value to set
Value to set
RM0090