Table 133. Error Calculation For Programmed Baud Rates At F; Oversampling By 16; Pclk = 8 Mhz Or F Pclk = 12 Mhz - STMicroelectronics STM32F405 Reference Manual

RM0090
Then, USART_BRR = 0x195 => USARTDIV = 0d25.625
Example 3:
To program USARTDIV = 0d50.99
This leads to:
DIV_Fraction = 8*0d0.99 = 0d7.92
The nearest real number is 0d8 = 0x8 => overflow of the DIV_frac[2:0] => carry must be
added up to the mantissa
DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33
Then, USART_BRR = 0x0330 => USARTDIV = 0d51.000

Table 133. Error calculation for programmed baud rates at f

Baud rate7
S.No Desired
1 1.2 KBps
2 2.4 KBps
3 9.6 KBps
4 19.2 KBps 19.185 KBps
5 38.4 KBps 38.462 KBps
6 57.6 KBps 57.554 KBps
7 115.2 KBps 115.942 KBps
8 230.4 KBps 228.571 KBps
9 460.8 KBps 470.588 KBps
10 921.6 KBps
11 2 MBps
12 3 MBps
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
Universal synchronous asynchronous receiver transmitter (USART)

oversampling by 16

Oversampling by 16 (OVER8=0)
f = 8 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
1.2 KBps 416.6875
2.4 KBps 208.3125
9.604 KBps 52.0625
26.0625
13
8.6875
4.3125
2.1875
1.0625
NA NA
NA NA
NA NA
DocID018909 Rev 11
PCLK
(1)
% Error =
(Calculated -
Actual
Desired) B.rate /
Desired B.rate
0 1.2 KBps
0.01 2.4 KBps
0.04 9.6 KBps
0.08 19.2 KBps
0.16 38.339 KBps
0.08 57.692 KBps
0.64 115.385 KBps
0.79 230.769 KBps
2.12 461.538 KBps
NA
NA
NA
= 8 MHz or f = 12 MHz,
PCLK
f = 12 MHz
PCLK
Value
programmed
in the baud
rate register
625
312.5
78.125
39.0625
19.5625
13
6.5
3.25
1.625
NA NA
NA NA
NA NA
% Error
0
0
0
0
0.16
0.16
0.16
0.16
0.16
NA
NA
NA
973/1731
1010