Dma Stream X Fifo Control Register (Dma_Sxfcr) (X = 0..7) - STMicroelectronics STM32F405 Reference Manual

RM0090
Bits 31:0 M1A[31:0]: Memory 1 address (used in case of Double buffer mode)
10.5.10

DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)

Address offset: 0x24 + 0x24 × stream number
Reset value: 0x0000 0021
31 30 29 28
15 14 13 12
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 FEIE: FIFO error interrupt enable
Bit 6 Reserved, must be kept at reset value.
Base address of Memory area 1 from/to which the data will be read/written.
This register is used only for the Double buffer mode.
These bits are write-protected. They can be written only if:
– the stream is disabled (bit EN= '0' in the DMA_SxCR register) or
– the stream is enabled (EN='1' in DMA_SxCR register) and bit CT = '0' in the
DMA_SxCR register.
27 26 25
11 10 9
Reserved
This bit is set and cleared by software.
0: FE interrupt disabled
1: FE interrupt enabled
DocID018909 Rev 11
24 23 22 21
Reserved
8 7 6 5
FEIE
Reser
ved
rw r
DMA controller (DMA)
20 19 18
4 3 2
FS[2:0] DMDIS
r r rw
17 16
1 0
FTH[1:0]
rw rw
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