Adc Regular Data Register (Adc_Dr) - STMicroelectronics STM32F405 Reference Manual

Analog-to-digital converter (ADC)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 JDATA[15:0]: Injected data

13.13.14 ADC regular data register (ADC_DR)

Address offset: 0x4C
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Regular data
13.13.15 ADC Common status register (ADC_CSR)
Address offset: 0x00 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
This register provides an image of the status bits of the different ADCs. Nevertheless it is
read-only and does not allow to clear the different status bits. Instead each status bit must
be cleared by writing it to 0 in the corresponding ADC_SR register.
31 30 29 28
15 14 13 12
OVR2 STRT2
Reserved
r
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 OVR3: Overrun flag of ADC3
Bit 20 STRT3: Regular channel Start flag of ADC3
428/1731
These bits are read-only. They contain the conversion result from injected channel x. The
data are left -or right-aligned as shown in
27 26 25
11 10 9
r r r r
These bits are read-only. They contain the conversion result from the regular
channels. The data are left- or right-aligned as shown in
Figure 49.
27 26 25
Reserved
11 10 9
JSTRT
JEOC2 EOC2
2
ADC2
r r r r
This bit is a copy of the OVR bit in the ADC3_SR register.
This bit is a copy of the STRT bit in the ADC3_SR register.
DocID018909 Rev 11
Figure 48
24 23 22
Reserved
8 7 6
DATA[15:0]
r r r
24 23 22
OVR3
8 7 6
AWD2 OVR1
Reserved
r
and Figure 49.
21 20 19 18
5 4 3 2
r r r r
Figure 48
21 20 19 18
STRT3 JSTRT3 JEOC 3 EOC3
ADC3
r r r r
5 4 3 2
STRT1 JSTRT1 JEOC 1 EOC1
ADC1
r r r r
RM0090
17 16
1 0
r r
and
17 16
AWD3
r r
1 0
AWD1
r r