Figure 110. External Trigger Input Block; Figure 111. Control Circuit In External Clock Mode 2; Capture/Compare Channels - STMicroelectronics STM32F405 Reference Manual

Advanced-control timers (TIM1&TIM8)
ETR pin
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
17.3.5

Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 112
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
528/1731

Figure 110. External trigger input block

ETR
0
divider
/1, /2, /4, /8
1
ETP ETPS[1:0]
TIMx_SMCR TIMx_SMCR

Figure 111. Control circuit in external clock mode 2

f
CK_INT
CNT_EN
ETRP
ETRF
Counter clock = CK_CNT = CK_PSC
Counter register
to Figure 115 give an overview of one Capture/Compare channel.
DocID018909 Rev 11
ETRP
filter
downcounter
f
DTS
ETF[3:0]
TIMx_SMCR
ETR
34
RM0090
TI2F
or
or
or
TI1F encoder
mode
TRGI external clock
mode 1
ETRF
external clock
mode 2
CK_INT
internal clock
mode
(internal clock)
ECE SMS[2:0]
TIMx_SMCR
35 36
CK_PSC