Rtc Initialization And Status Register (Rtc_Isr) - STMicroelectronics STM32F405 Reference Manual

Real-time clock (RTC)
Bit 4 REFCKON: Reference clock detection enable (50 or 60 Hz)
Note: PREDIV_S must be 0x00FF.
Bit 3 TSEDGE: Timestamp event active edge
Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection
Note: WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when
WUCKSEL[2:1 = 11].
Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).
Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR
WUTWF bit = 1.
It is recommended not to change the hour during the calendar hour increment as it could
mask the incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.
This register is write protected. The write access procedure is described in
write protection on page
26.6.4

RTC initialization and status register (RTC_ISR)

Address offset: 0x0C
Backup domain reset value: 0x0000 0007
System reset value: Not affected except INIT, INITF and RSF which are cleared to 0.
31 30 29
15 14 13
TAMP TAMP
Res. TSOVF
2F 1F
rc_w0 rc_w0 rc_w0
810/1731
0: Reference clock detection disabled
1: Reference clock detection enabled
0: TIMESTAMP rising edge generates a timestamp event
1: TIMESTAMP falling edge generates a timestamp event
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
000: RTC/16 clock is selected
001: RTC/8 clock is selected
010: RTC/4 clock is selected
011: RTC/2 clock is selected
10x: ck_spre (usually 1 Hz) clock is selected
11x: ck_spre (usually 1 Hz) clock is selected and 2
(see note below)
794.
28 27 26 25
12 11 10 9
TSF WUTF ALRBF ALRAF
rc_w0 rc_w0 rc_w0
DocID018909 Rev 11
24 23 22
Reserved
8 7 6
INIT INITF
rc_w0 rw r rc_w0
16
is added to the WUT counter value
RTC register
21 20 19 18
5 4 3 2
WUT
RSF INITS SHPF
WF
r r r
RM0090
17 16
RECAL
PF
r
1 0
ALRB ALRA
WF WF
r r