Flexible static memory controller (FSMC)
The differences with mode1 are the toggling of NWE and the independent read and write
timings when extended mode is set (Mode B).
1546/1731
Figure 439. Mode2 write accesses
A[25:0]
NADV
NEx
NOE
NWE
D[15:0]
Figure 440. Mode B write accesses
A[25:0]
NADV
NEx
NOE
NWE
D[15:0]
HCLK cycles
DocID018909 Rev 11
Memory transaction
ADDSET
HCLK cycles
Memory transaction
data driven by FSMC
ADDSET
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
1HCLK
(DATAST + 1)
HCLK cycles
RM0090
ai15562
ai15563
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